SUNNYVALE, Calif. – Garnering support from one of the industry’s leading innovators in electronic design automation (EDA), the HyperTransport Technology Consortium has said that (NASDAQ:CDNS [1]) Cadence Design Systems, Inc. has joined the Consortium. Cadence plans to offer the industry’s lowest latency, customizable HyperTransport 3.0 interconnect PHY cores as part of its Cadence Services business, making them accessible to customers in a wide range of markets including consumer electronics, networking and telecommunications equipment and computer systems.

“Our goal is to empower designers to create leading-edge integrated circuits, boards and systems through our industry-leading EDA technologies and services,” said Tim Henricks, vice president for Services at Cadence. “Our customers recognize the significant performance advantages that the HyperTransport interconnect offers, and our Consortium membership ensures we provide them with proper validation tools and technologies required to meet their performance and ease-of-design needs.”

HyperTransport 3.0, the latest version of the HyperTransport interconnect standard, extends the dual data rate (DDR) maximum clock to 2.6 GHz, and delivers a maximum aggregate bandwidth of 41.6 Gbps. The standard is being widely adopted by manufacturers, and has helped the standard reach considerable market presence and success.

“We welcome Cadence as a new Consortium member, and look forward to working with them to extend the roster of HyperTransport-based IP and system design solutions available to the industry,” said Mario Cavalli, general manager of the HyperTransport Consortium.“ The addition of this high-profile EDA company to our membership roster validates the tremendous value and momentum behind the HyperTransport standard.”